Knowledge Center

Knowledge Center

Monolithic 3D Chips

A way of stacking transistors inside a single chip instead of a package.


Monolithic 3D integrated circuits are being investigated by IBM, CEA-Leti, MonolithIC 3D, Qualcomm and many others.

In advanced 2.5D/3D stacked-die, bare die are connected using through silicon vias (TSVs). In contrast, monolithic 3D integration involves a process of stacking, aligning and connecting leading-edge transistors on top of each other to form a monolithic 3D chip. Using standard vias, monolithic 3D ICs are said to provide 10,000 times more connections at smaller feature sizes than stacked 2.5D/3D TSV technology.

Monolithic 3D integration was conceived several decades ago, but over the years, a number of entities have tried but failed to get the technology to work. In the technology, there are restrictive thermal budget for anneals, deposition and epi. Annealing is the most challenging problem.

Now, the industry is beginning to address some of the challenges, making monolithic 3D chips a possible contender for the 7nm node and beyond. Today, in the lab, researchers have made some progress, claiming the ability to stack two layers of leading-edge transistors on each other.

There are several different types of fabrication flows for monolithic 3D integration. For example, in one flow from MonolithIC 3D, a chipmaker would first develop a conventional CMOS wafer, which would have transistors and copper interconnects. Then, the chipmaker would obtain a separate wafer or donor wafer.

That wafer goes through an oxidation and implantation process. A hydrogen layer creates a layer of damage in the single crystal silicon. Then, the donor wafer is flipped over and bonded on top of the original CMOS processed wafer using an oxide-to-oxide bonding process, according to MonolithIC 3D. At that point, the top of the structure is then cleaved or indented using either mechanical force or annealing, according to the company.

Then, a chipmaker would form transistors on the top of the donor wafer, which is aligned and stacked on top of the bottom transistors. To form transistors on the top structure, a chipmaker would form so-called “recessed channel transistors” (RCATs) using etch and deposition tools. Then, the gate stack is formed, followed by the interconnects.

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