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Soft IP

Synthesizable IP block
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Description

Soft IP is delivered as a Verilog or VHDL functional model that can go through the synthesis and implementation flows of the IP consumer. In addition, the IP developer will provide the verification environment that was used to verify the functional behavior of the device. They may also supply sample scripts that could be used for turning the soft IP into a physical implementation, a process called hardening.

Along with the IP will be a substantial amount of document such as user’s guides, test guides, integration manuals etc. This can be supplied in textual form, or as is becoming more common in a number of standard formats that add rigor to the way in which the block is documented. Examples are IP-XACT for connectivity information, IEEE 1801 (UPF) for power information etc.

Increasingly abstract behavioral models are being requested for integration into virtual prototypes. These enable fast system-level simulation be performed and for software to be executed on the complete chip.


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