The use of metal fill is a traditional, and mandatory, part of the IC design flow. Initially, metal fill was used to improve planarity. Fill involves adding shapes or polygons to the design that are structural, not logical. Fill gives a more even distribution of metal across the die by adding non-functional metal shapes to open regions in a design. This uniformity of metal density helps reduce thickness variations that occur during chemical-mechanical polishing (CMP).
In older technology nodes, fill was added and often called floating or dummy fill. However, fill can affect timing and signal integrity, effects that are more amplified in the smaller geometries. As with these smaller geometries, design rules are a lot more complex, requiring that fill is handled earlier in the implementation process.
In addition to improving planarity, fill can now be used to manage electrochemical deposition (ECD), etch, lithography, stress effects, and rapid thermal annealing (RTA). This new role for metal fill in managing the impacts of manufacturing variation also includes understanding and managing the timing effects of added fill.
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