Substrate biasing in PMOS biases the body of the transistor to a voltage higher than Vdd; in NMOS, to a voltage lower than Vss.
Since leakage currents are a function of device Vth, substrate biasing—also known as back biasing—can reduce leakage power. With this advanced technique, the substrate or the appropriate well is biased to raise the transistor thresholds, thereby reducing leakage. In PMOS, the body of transistor is biased to a voltage higher than Vdd. In NMOS, the body of transistor is biased to a voltage lower than Vss.
Since raising Vth also affects performance, an advanced technique allows the bias to be applied dynamically, so during an active mode of operation the reverse bias is small, while in standby the reverse bias is stronger.
Area and routing penalties are incurred. An extra pin in the standard cell library is required and special library cells are necessary. Body-bias cells are placed throughout the design to provide voltages for transistor bulk. To generate the bias voltage, a substrate-bias generator is required, which also consumes some dynamic power, partially offsetting the reduced leakage.
Substrate bias returns are diminishing at smaller processes in advanced technologies. At 65nm and below, the body-bias effect decreases, reducing the leakage control benefits. TSMC has published information pointing to a factor of 4× reduction at 90nm, and only 2× moving to 65nm. Consequently, substrate biasing is predicted to be overshadowed by power gating.
For single-well technology, the bulk of the PMOS is connected to the n-well and the bulk of the NMOS is connected to the p-substrate. For dual-well technology, the bulk of the NMOS is connected to a p-well.
Depending on the library, substrate biasing can be done for the PMOS, NMOS, or both. To bias the bulk of the NMOS and PMOS of the standard cells, voltages are created by charge pumps, which are custom blocks that output VDDbias and VSSbias voltages.
These charge pumps, which are custom macros about the size of PLLs, provide VDDbias and VSSbias. These voltages then need to be distributed across the parts of the chip that utilize substrate biasing. There are two methods for distributing the bias voltages to standard cells:
1) Using well-tap cells (body-bias cells)
2) In-cell taps, having VDDbias and VSSbias pins for each standard cell, then tapping those pins to n-well and p-sub, respectively
Well-Tap or Body-Bias Cells
Well-tap or body-bias cells tap VDDbias and VSSbias to n-well and p-sub, respectively. Theoretically, each standard cell row must have at least one well-tap cell. In reality, multiple body-bias or well-tap cells are needed per standard cell row to prevent latch-up. Designers usually have a rule of one tap cell placed in a standard cell row per every certain distance, at regular intervals.
Adding well-tap cells actually saves area, because compared with the second method listed below, the only area increase is for the well-tap cells (which are smaller than the average 1x inverter).
A typical body-bias cell looks similar to a normal non-bias cell, except for two differences: The n-well is tapped to VDDbias instead of Vdd, and the p-sub is tapped to VSSbias instead of Vss
. Placing this cell at multiple points in every standard cell row will tap the n-well and p-sub of that row to VDDbias and VSSbias, respectively.
In-cell taps means having VDDbias and VSSbias pins for each standard cell, then tapping those pins to the n-well and p-sub, respectively. Extra pins are used to connect VDDbias and/or VSSbias to n-well and p-substrate, respectively, in each standard cell.
This method provides a consistent bias voltage level to the n-well and p-sub, but uses more area, since each standard cell has to reserve area for the bias voltage pins as well as the tap area. It also takes up a significant amount of routing resources, due to the need for routing every VDDbias and VSSbias pin to the bias voltage sources.
A standard cell that employs VDDbias and VSSbias pins is shown below. Here, the separate body-bias cell is not needed, because the taps to n-well and p-sub are embedded in the standard cells. Each standard cell has an extra VDDbias and VSSbias pin, which is connected to metal shapes. The metal shapes are then tapped to n-well and p-sub.
Potential Issues with Substrate Biasing
Designers who choose to utilize substrate biasing may run into two potential issues, involving p-substrate separation and bias voltage distribution.
For single-well technologies, the entire chip silicon is
the p-substrate. That is, except for the parts of the chip that have been made into the n-well, the entire chip die is essentially the p-sub. That means if the designer chooses to bias the p-substrate, the entire substrate of the chip would be biased. This is rarely desirable, because usually certain parts of the chip (for example, any analog blocks) should not be biased.
This is not a problem for n-well biasing, since the n-well of the chip is easily separated.
This is also not a problem for dual-well technologies, which have a p-well and n-well. Therefore, the p-well can be separated from the rest of the chip, just like the n-well.
Bias Voltage Distribution
Regardless of the bias voltage distribution method, the bias voltage nets (VDDbias and VSSbias) still have to be routed from the charge pump to the well-tap cells or standard cells. Most EDA tools today do not have special functionality for substrate biasing. Therefore, the designer might run into issues while routing the bias voltage distribution nets.
More important, these distribution nets take up a significant amount of routing resources and might adversely affect the routability of the design.
An alternative to substrate biasing is diffusion biasing, which bypasses the substrate separation issue. In this technique, the diffusion of the transistor is biased instead of the bulk.
Note that as processes shrink, substrate biasing is predicted to be overshadowed by power shutdown. This is because the power-saving returns for substrate biasing are diminishing with smaller processes, thereby making PSO a more attractive choice.
On a sample of designs, substrate biasing has shown a 10X reduction in leakage power. It can result in a 10% timing penalty and an area penalty of less than 10%. The impact on implementation can be significant.
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