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SystemVerilog

Industry standard design and verification language
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Description:

SystemVerilog is a combination of a hardware description language (HDL), based on Verilog and a hardware verification language (HVL) based on Vera with additional features coming from assertion languages. Apart from being under a single name and sharing a similar low level syntax, SystemVerilog remains a collection of different languages.

The HDL portion of the language comes from IEEE 1364-2001 which is now technically deprecated in favor of SystemVerilog (IEEE 1800). It is extended with some features of VHDL such as interfaces. New Application programming interfaces were added including the Direct Programming Interface (DPI).

The HVL itself is multiple languages. The main body is an objected oriented language that targets a constrained random test pattern methodology. The assertion language is a declarative language that has now been essentially converged with the property specification language (PSL).

SystemVerilog 3.0 (The initial release was 3.0 because they argued that the original Verilog was 1.0, 1364-2001 was Verilog 2.0 and so this was Verilog 3.0) was approved by Accellera in June 2002 and turned over to the IEEE for ratification.

SystemVerilog Version 3.1 was released in May 2003 and version 3.1a in May 2004 which included improvements in the verification language and C language integration. This became IEEE 1800-2005.

IEEE 1800-2009 (December 2009) brought the Verilog portion of the standard up to IEEE 1364-2005 and this formally ended development of future Verilog versions. The latest version is IEEE 1800-2012 which is available free of charge under the IEEE Get Program.

Due to the extensiveness of SystemVerilog, EDA vendors were not able to implement the entirety of the language in a single release. In order to facilitate usage of the subset each of them had implemented, they developed methodologies and class libraries around their subset to assist users creating a verification environment. This led to a plethora of methodologies such as Verification Methodology Manual (VMM) from Synopsys, The Advanced Verification Methodology (AVM) from Mentor and others. Over time these converged until the industry finished up with Universal Verification Methodology (UVM).

Related Books
Logic Design and Verification Using SystemVerilog

SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications

A SystemVerilog Primer



  • Other names: IEEE 1800
  • Type: EDA

Relationships:

  • SystemVerilog was invented by Accellera in 2002
    • SystemVerilog 3.0 released June 2002

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