Knowledge Center

Knowledge Center


A memory architecture in which memory cells are designed vertically instead of using a traditional floating gate.


Thanks to 193nm immersion and multiple patterning, flash vendors have extended planar NAND down to the 1xnm node regime. Planar NAND involves the production of horizontal strips of polysilicon. The strips are used to make the wordlines. These, in turn, connect the control gates of the memory cells.

But at the 1xnm node, vendors are struggling to scale the critical element in a NAND device—the floating gate. In fact, the floating gate is seeing an undesirable reduction in the control gate to capacitive coupling ratio.

Realizing that planar NAND is on its last legs, Samsung in 2013 got a jump on its rivals and introduced the industry’s first 3D NAND device. Samsung’s V-NAND device is a 128 Gbit chip, which stacks 24 vertical layers and consists of 2.5 million channels. More recently, Samsung introduced a 32-layer device and SSDs based on its chips.

In addition, Micron, SK Hynix and Toshiba are also developing 3D NAND.

In 3D NAND, the polysilicon strips are stretched, folded over and stood up vertically. Instead of using a traditional floating gate, 3D NAND uses charge trap technology. Based on silicon nitride films, charge-trap stores the charge on opposite sides of a memory.

One way to illustrate the manufacturing challenges for 3D NAND is to examine Samsung’s V-NAND device. Using 30nm to 40nm design rules and a gate-last flow, Samsung’s 3D NAND technology is called the Terabit Cell Array Transistor (TCAT). TCAT is a gate-all-around device, where the gate surrounds the channel.

The TCAT flow starts with a CMOS substrate. Then, alternating layers of silicon nitride and silicon dioxide are deposited on the substrate, according to Objective Analysis. This process, which is like making a layer cake, represents the first big challenge in the flow—alternating stack deposition.

Using chemical vapor deposition (CVD), alternating stack deposition involves a process of depositing and stacking thin films layer by layer. The challenge is to deposit the films with good uniformities and low defects. And the challenges escalate as 3D NAND vendors scale their devices beyond 32 layers.

Alternating stack deposition determines the number of layers for a given device. Following that step, a hard mask is applied on the structure and holes are patterned on the top.

Then comes the next hard part. High-aspect ratio trenches are etched from the top of the device to the substrate. The aspect ratios are ten times larger than those in planar. Following the high-aspect ratio etch process, the hole is lined with polysilicon for the channel. The hole is filled with silicon dioxide, which is called a “macaroni channel,” according to Objective Analysis.

Then, columns are formed within the structure using a slit etch process. At that point, the original alternating layers of silicon nitride and silicon dioxide are removed. The final structure looks like a narrow tower with fins, according to Objective Analysis.

Following that step, the peripheral logic must be connected to the control gates. To accomplish that feat, the structure undergoes another difficult step—staircase etch. Using an etcher, the idea is to etch a staircase pattern into the side of the device.

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