In the BEOL, there are many process steps, which fall into two categories—patterning and the dual damascene process. Initially, in the flow, each level of a given chip structure must be patterned to create the wiring schemes. For this, chipmakers use 193nm immersion and multiple patterning.
The copper dual damascene process involves three main parts—metallization; low-k dielectrics; and the capping layer.
In the metallization step, a structure undergoes a diffusion barrier etch step. Then, a via dielectric is deposited. An etch step then forms a gap, where the lines and vias are formed.
Then, a thin barrier layer of tantalum (Ta) and tantalum nitride (TaN) materials are deposited using physical vapor deposition (PVD). Ta is used to form the liner and TaN is for the barrier. The barrier layer is coated over by a copper seed barrier.
Finally, the structure is electroplated with copper and ground flat using chemical mechanical polishing.