FDSOI uses an ultra-thin layer of silicon over a buried oxide as a means to reduce leakage and variation in chips. FDSOI also boasts a back-bias feature.
Silicon-on-insulator (SOI) technology itself refers to the use of a layered SOI substrate in place of a conventional bulk substrate. Fully-depleted silicon-on-insulator (FDSOI) relies on an ultra-thin layer of an insulator, called the buried oxide. This is placed on top of the base silicon.
There is no need to dope the channel. This, in turn, makes the transistor fully depleted. One knock on FDSOI is the cost. SOI substrates are more expensive than bulk CMOS wafers.
Recently, the SOI industry has revised its FDSOI roadmap. Previously, the industry planned to extend planar FDSOI for three generations from 28nm, to 14nm, and then to 10nm. 20nm FDSOI was not on the industry’s roadmap. Then, the industry would offer finFETs on SOI at 7nm.
Now, the industry is developing a 20nm FDSOI process. And IBM plans to field finFETs on SOI at 14nm and 10nm.
The most compelling market for FDSOI resides at the 28nm node. 28nm is expected to be a long-running node. But the bulk CMOS camp won’t give up the 28nm market so easily. TSMC, for example, recently expanded its process lineup with a new and cheap 28nm bulk CMOS derivative.
Recently, IBM described an SOI finFET technology, which is said to be a more simple process than bulk finFETs. “Once a wafer with the desired thickness is available, formation of the fin is simple," according to a recent paper from IBM. "In contrast, forming a fin of a desired dimension in a bulk substrate requires at least three additional steps of fill, polish, and etch. Although significant progress has been made in improving the control of the bulk process, the fundamental control capability in bulk is still three times worse than SOI.”
Of course, there are a multitude of trade-offs between bulk versus SOI finFETs. SOI suffers from potential cost and ecosystem issues. “Two potential concerns for SOI-based finFETs have been the effect of self-heating and a shortfall in the ability to exert strain on the channel from the source/drain region,” according to IBM. “While both of these aspects may be of some interest at the 10nm node, the future direction of technology renders these issues moot – not so much because SOI finFETs will be less susceptible to these concerns, but rather because bulk devices will become more so.”