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Simulation

A simulator exercises of model of hardware
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Description

A simulator is a piece of software that exercises a model of hardware. It can be written using several levels of abstraction and use a variety of languages. For example an analog model of the system is probably written at a very detailed level of abstraction in a language called SPICE and executed by a simulator of the same name. Most digital models today are written using an abstraction called register transfer level (RTL) using either the Verilog or VHDL languages. More recently SystemC has emerged as a language for modeling systems in a more abstract manner. Most commercial simulators accept multiple abstractions and languages although few support all of them.

Assuming you have a model, the simulator will exercise that model and observe its behaviors based on the stimulus that is supplied to it. For an act of verification, you need to ensure that the design behaves as intended. The collection of stimulus, checkers, coverage, constraints and result predictor is called a testbench.


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