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Electromigration

Electromigration (EM) due to power densities
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Description

Electromigration, which can cause voids and failures in a device, refers to the displacement of the atoms as a result of current flowing through a conductor. To suppress electromigration in the interconnect part of the equation, chipmakers typically use a capping or etch stop layer of material on a dual-damascene structure.

But some warn the conventional capping layer of materials in advanced designs—silicon carbon nitride (SiCN) and a copper alloy—could run out of steam at 20nm and beyond, prompting the need for a new solution.

There are several new capping layer options for advanced designs. One solution is to somehow extend the current materials. Another option is Lam Research’s electroless deposition technology, which deposits cobalt-tungsten-phosphide (CoWP) or a related material. This is already in production in at least one foundry vendor at 32nm.

And a newer option is Applied Materials’ in-situ metal/dielectric tool technology for use in depositing cobalt and SiCN. Cobalt-related materials are said to boost electromigration lifetimes by up to hundredfold.

It’s still too early to tell which capping technology will prevail in the long run. The capping layer process takes place during the formation of the interconnect in the dual-damascene flow.

The dual-damascene flow includes the following steps: via and trench patterning, barrier layer and copper seed deposition, electroplating and chemical mechanical polishing. Using a deposition technique, the final step in the process is the addition of a capping layer. This is because the interface between the copper line and capping layer is susceptible to electromigration.

Prior to the 90nm node, IC makers generally used silicon nitride (SiN) as the capping layer material. At 130nm and 90nm, chip makers also moved to low-k materials. The trouble was that the dielectric constant of SiN was more than double that of low-k films, which impacted the overall effective k value of the stack.

This, in turn, prompted chipmakers to switch to SiCN materials for the capping layer as a means to reduce capacitance at or around 90nm. SiN has a dielectric constant of 7.0, while SiCN is around 5.0.

The next big material, cobalt, has been proposed because it adheres well to copper. In a structure, IC makers would still use SiCN as the outside metal capping layer. A thin layer of cobalt serves as the interface between the copper and SiCH. Cobalt helps to suppress electromigration, but it adds cost to the equation. So does electroless deposition, which can deposit various materials, such as CoWP, nickel molybdenum phosphide (NoMP) and others, but at the cost of additional processing steps.


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