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Epitaxy

A method for growing or depositing mono crystalline films on a substrate.
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Description

Epitaxy is a method to grow or deposit monocrystalline films on a structure or surface. There are two types of epitaxy—homoepitaxy and heteroepitaxy. Homoepitaxy is a process in which a film is grown on a substrate of the same composition. Heteroepitaxy is a film that is grown on a substrate, which has a different composition.

Epitaxial silicon is grown using vapor-phase epitaxy (VPE). This is a modification of chemical vapor deposition (CVD). Another technology, molecular-beam epitaxy (MBE), is mainly for compound semiconductors. MBE is a slow, line-of-sight technique, not suitable for filling trenches and other three-dimensional structures.

For silicon processes, epitaxy is used in source-drain and strain engineering techniques. They are also playing a big role in the channel in chip designs.

The big change in the channel took place at 90nm, when the industry introduced strain engineering in the region. Using a blanket epitaxial process, chipmakers integrated silicon-germanium (SiGe) stressors, or distortions in the crystal lattice, in PMOS transistors. This, in turn, boosted hole mobility and drive current.

Using the same epi process, chipmakers are moving towards strain engineering for the NMOS starting at 20nm. The NMOS transistors require a tensile strain, enabling a boost in drive current.

Still, today’s strained-silicon technology is under stress. So, chipmakers may need to make a materials change in the channels at 10nm or 7nm. At one time, the leading candidate was germanium (Ge) for PMOS and indium-gallium-arsenide (InGaAs) for NMOS. (Ge has an electron mobility of 3,900cm-square-over-Vs, compared to 1,500cm-square-over-Vs for silicon. InGaAs has an electron mobility of 40,000cm-square-over-Vs.)

Ge and III-V are fast but difficult to implement due to the lattice mismatch with silicon. Now, the industry is looking at a simpler approach. Chipmakers will likely use SiGe for PMOS at 10nm or 7nm, depending on the company and requirements. For NMOS, the industry may stick with tensile silicon.

In any case, there are two main approaches in terms of depositing Ge, SiGe or III-V materials in the channels-—blanket and selective epi. The blanket approach calls for the epi materials to be grown everywhere on the surface. In selective, the epi materials are only grown on a select part of the surface.

At present, some prefer the traditional blanket approach. The blanket approach has some drawbacks, however. With blanket epi, a chipmaker may end up depositing materials on unwanted regions. In that case, the IC vendor must etch away those materials. All told, blanket epi may have more process steps, possibly making it more expensive.

For that reason, selective epi is also viable. In selective, a tool can mix and match materials with other types of materials. But in some respects, it is far more complex than blanket epi.

Imec, for one, has demonstrated a selective growth process, depositing germanium and InGaAs pillars into patterned oxide trenches to make a “virtual substrate” for device fabrication. Using this technique, Imec demonstrated what it believes to be the first III-V finFETs integrated epitaxially on 300mm silicon wafers.

Imec’s process starts by using standard shallow trench isolation processes to create a template, with pillars of silicon surrounded by silicon dioxide. Then, a silicon dioxide cap is deposited over the areas where InGaAs will ultimately go. In the uncapped regions, the silicon pillars are etched away, and the exposed trenches filled with germanium. Next, the germanium is capped with silicon dioxide and the InGaAs areas are exposed.

InGaAs pillar formation begins by etching out the silicon pillars to create a concave bottom surface, slightly wider than the ultimate trench width. Successive depositions of germanium, InP, and InGaAs follow, gradually accommodating the lattice mismatch between silicon and InGaAs. The narrow trenches are key to this process: because of the rounded bottom surface, dislocations tend to form at an angle to the sides of the trench, and are trapped against the sidewalls rather than propagating through the InP and InGaAs bulk. An active layer with acceptable quality is achieved with a thinner, less time-consuming deposition. Moreover, with selective deposition there is no need to etch InGaAs, or to dispose of toxic arsenic-based etch by-products.


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