Knowledge Center

Knowledge Center


A way to image IC designs at 20nm and below.


Multiple patterning is a technique that overcomes the lithographic limitations in the chip-manufacturing process. Today’s single-exposure, 193nm wavelength lithography reached its physical limit at 40nm half-pitch. Multiple patterning enables chipmakers to image IC designs at 20nm and below.

Basically, there are two main categories of multiple patterning—pitch splitting and spacer. Pitch splitting is an umbrella term, which includes double patterning and triple patterning techniques. Meanwhile, spacer involves self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP). Both pitch splitting and spacer techniques can be extended to octuplet patterning.

The first type, pitch splitting, is mainly used in logic. The most common form of pitch splitting is double patterning. “On the design side, ‘double patterning’ almost always refers to the litho-etch-litho-etch (LELE) pitch-splitting process,” according to Mentor Graphics. In the fab, LELE requires two separate lithography and etch steps to define a single layer. LELE provides a 30% reduction in pitch, according to Sematech. But LELE can be expensive, as it doubles the process steps in the lithography flow.

Initially, this technique separates the layouts that cannot be printed with a single exposure, forming two lower-density masks. Then, it uses two separate exposure processes. This, in turn, forms two coarser patterns. They are combined and superimposed, which enables a single finer image on the wafer.

LELE, or double patterning, imposes new layouts, physical verification and debug requirements on the designer. For example, on the design side, the mask layers are assigned colors, based on spacing requirements. The mask layers are split, or decomposed, from the original drawn layout into two new layers.

One key methodology decision is as basic as whether or not you want the designers to see colors at all—called a “colorless” design flow. The alternative is a two-color flow, in which the designer tapes out two masks, choosing one of several decomposition options. Of course, there are trade-offs with any design flow.

At 20nm, foundries are using several different double patterning design flows. One of the more common flows does not actually require the design team to decompose their layers into two colors. However, there are situations in which the designer may want to know what the color assignments will be. As reasonable as this may sound, seeing the double patterning colors will most likely degrade debug productivity.

Meanwhile, at the 10nm node, chipmakers may need to move to another pitch splitting technique—triple patterning. One form of triple patterning is litho-etch-litho-etch-litho-etch (LELELE). LELELE is similar to LELE. In the fab, LELELE requires three separate lithography and etch steps to define a single layer.

On the design side, triple patterning requires decomposition of the original layer into three masks. The shapes from the three masks are combined during manufacturing to create the final shapes. Triple patterning may look innocuous from the outside, but potential chaos lies just within. It’s challenging to build an EDA software algorithm for automating the decomposition, or coloring, and checking of a layer using triple patterning. Triple patterning violations can be quite complex, and debugging can be difficult.

Meanwhile, spacer is the second main category for multiple patterning. It is also referred to as SADP and SAQP. SADP/SAQP, which have been used to extend NAND flash memory to the 1xnm node, is now moving into logic.

SADP is a form of double patterning. It is sometimes referred to as pitch division or sidewall-assisted double patterning. The SADP process uses one lithography step and additional deposition and etch steps to define a spacer-like feature. In the SADP process, the first step is to form mandrels on a substrate. Then, the pattern is covered with a deposition layer. The deposition layer is then etched, which, in turn, forms spacers. Finally, the top portion undergoes a chemical mechanical polishing (CMP) step.

SAQP is basically two cycles of the sidewall spacer double patterning technique. Simple patterns, including those in flash memory or the fins in finFETs, are done in SADP or SAQP. In this technique, lone parallel lines are formed, followed by cuts. Meanwhile, metal levels in DRAM and logic chips are more complex and can’t be done with SADP/SAQP. These metal layers require LELE. SADP/SAQP also have less design flexibility than LELE. Hole-type patterns are required for LELE-type technology.

Page contents originally provided by Mentor Graphics Corp.


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