Basic building block for both analog and digital circuits.
When a MOSFET transistor turns on, the gate capacitor applies an electric field to the channel, creating an inversion layer. This allows minority carriers (holes in pFETs, electrons in nFETs) to flow between the source and the drain. When the transistor is off there is no capacitance: the energy barriers between the source, drain, and channel prevent current flow. As transistors shrink, the electric field density needed to create the inversion layer increases, and so the gate capacitance must increase. Up to a point, this is accomplished by reducing the thickness of the gate dielectric. As the gate dielectric thickness falls to only a few nanometers, however, quantum mechanical effects allow carriers to tunnel through it, increasing gate leakage and ultimately shorting the transistor.
Silicon transistors already have confronted this issue, which led to the introduction of high-k gate dielectric materials. As the dielectric constant (k) increases, the same capacitance is achieved with a thicker physical layer. Designers can minimize leakage while getting the electrostatic control they need.
In the near term, the leading-edge chip roadmap looks fairly clear. Chips based on today’s finFETs and planar fully depleted silicon-on-insulator (FDSOI) technologies are expected to scale down to the 10nm node. But then, the CMOS roadmap becomes foggy at 7nm and beyond.
The industry has been exploring a number of next-generation transistor candidates. At 7nm, for example, the leading contender is the high-mobility finFET, which makes use of III-V materials in the channels to boost the mobilities. The electron mobilities for today’s silicon-based finFETs degrade at 7nm. Germanium (Ge) and III-V materials have higher electron transport capabilities, allowing for faster switching speeds. The first III-V finFETs will likely consist of Ge in the PFET, according to experts. Then, the next-generation III-V finFETs may consist of Ge for PFET and indium gallium arsenide (InGaAs) for NFET.
At 5nm, two technologies—gate-all-around field-effect transistor and tunnel field-effect transistor (TFET)—are taking a narrow lead. Considered the ultimate CMOS device in terms of electrostatics, gate-all-around is a device in which a gate is placed on all four sides of the channel. In contrast, TFETs are steep sub-threshold slope transistors aimed at low-power applications.